Semiconductor integrated circuits are quickly destroyed when subjected to excessive voltages. One of the most common causes of damage is electrostatic discharge or ESD. An ESD event occurs whenever a packaged IC is subjected to the dissipation of static electricity, which may occur whenever the pins of the IC come into contact with another surface. Thus, the likelihood of an ESD event damaging or destroying an IC is substantial during packaging and handling of the IC. Even after an integrated circuit is mounted on a circuit board and housed within a system, such as a modem or PC, it is nonetheless susceptible to ESD events discharging in and around the circuitry.
The human body is a major source of static charge. It is sometimes modeled as a 100 picofarad capacitor, capable of storing two or three kilovolts and having a series resistance on the order of a few K-ohms. Thus, when the pins of a packaged integrated circuit are touched by a person, a peak current on the order of two amperes can be delivered through the MOS devices on the IC. These voltages and currents can easily damage or destroy the gate oxides of modern MOS devices on the IC which have sub-micron geometries. To address this problem, most ICs are provided with some sort of ESD protection scheme.
Frequently, ESD protection schemes comprise one or more diodes or SCR circuits coupled between each input/output (I/O) pad on the chip, and the power supply rails. When an excessive voltage appears at the corresponding pin, for example an ESD event, the diode, SCR or similar circuitry turns on very quickly, to short the high voltage to the power supply node. For example, U.S. Pat. Nos. 4,829,350; 4,811,155; 4,855,620; and 4,692,834 all disclose ESD protection circuits in which the channel of an MOS device is coupled between ground and a pin of the IC. Such an MOS device has a parasitic bipolar transistor coupled in parallel with the MOS device. When a positive ESD event occurs at the pin, the bipolar transistor is forward-activated, and a substantial portion of the ESD current is passed through it to ground. An electrostatic discharge protection circuit having a non-lightly doped drain MOS device for protecting other lightly doped drain devices is disclosed in U.S. Pat. No. 5,246,872. A method for forming a silicon-controlled rectifier (SCR) in a semiconductor integrated circuit is described in U.S. Pat. No. 5,369,041. Another CMOS on-chip ESD protection circuit and related semiconductor structure are shown in U.S. Pat. No. 5,182,220.
Typically, the IC "chip" or die includes an I/O "slot" adjacent each bonding pad. Each slot is simply a predetermined area in which a selected I/O circuit, such as a buffer circuit, is formed when the rest of the chip is fabricated. Standard buffer circuits or "cells" are inserted from a cell library as needed. These buffer circuits generally include an ESD protection structure, as noted, but in any event the buffer must fit within the standard slot size. Since the level of ESD protection or immunity depends upon silicon area of the protection structure, the level of protection is limited by the I/O slot size on the die. This level of protection is often inadequate.
Moreover, the present inventor has observed that corner pins of an IC are adversely affected by ESD more often than the other pins. This is apparently due to the tendency of a high-voltage discharge to concentrate at the corners of the package. What is needed therefore is to improve ESD immunity in integrated circuits, without increasing silicon area dedicated to the task. What is also needed is to improve immunity particularly at corner pins, again without increasing silicon area.